==============================================================
Guild: wafer.space Community
Channel: Information / general / Planning schedule for wafer.space GF180MCU Run #2
After: 10/31/2025 23:59
Before: 12/01/2025 00:00
==============================================================

[11/07/2025 04:42] mithro_ (pinned)
With the deadline for GF180MCU Run #1 rapidly coming up, I'm starting to think about when / how to schedule GF180MCU Run #2. 

It is currently expected that Run #1 will come back in March 2026. I'm thinking it's best to have the closing time for Run #2 sometime after that so people can demonstrate working silicon.

I would love thoughts, suggestions, opinions on what type of timeline makes sense to people.

{Reactions}
💜 waferspace 👍 (2)

[11/07/2025 04:43] mithro_
@Leo Moser (mole99) / @urish / @Tholin - I assume you probably have opinions.....


[11/07/2025 07:12] 246tnt
I would think that waiting after run #1 is done and people had time to test is a good idea.  Unless there is is enough demand to completely fill a run #2 before that ( which I doubt ), I don't really see any benefit into making it before.


[11/07/2025 07:17] urish
Our current schedule for the first half of 2026 is:
- Mid March: TTIHP26a
- Early April: TTSKY26a
- Early June: TTSKY26b

So either Feb or early May would probably be good


[11/07/2025 08:49] tholin
Sounds sensible to me


[11/07/2025 09:05] mithro_
Random thought -- I was hoping to have ~4 runs in 2026


[11/07/2025 09:10] mole99
I agree with Sylvain. It would be good to be able to test designs before the next shuttle. And seeing the designs in action would be even more an incentive for people to buy a slot on the next shuttle.

Four runs might be quite a lot initially. Maybe you want to reduce them for 2026?


[11/07/2025 09:27] 246tnt
As an end goal, that seems fine, but when things are getting started, I wouldn't rush.
Beside the obvious "does it work" and "demo effect" :
(1) being the first run, there is also the question of how packaging / bonding will work out which might influence what people want to do for the next runs.
(2) I don't have the numbers, but I would expect the first few runs might end up being run at a loss and it might take time for people to get moving designing stuff, so not burning all capital before that happens would be good 😅


[11/16/2025 22:09] mithro_
Pinned a message.


[11/29/2025 01:29] dshadoff
I think demonstration of working designs - especially if any of them were available as references - would do a lot to encourage people to submit designs.


[11/29/2025 01:30] dshadoff
Ideally, somebody could put together a video with an overall workflow as well - for example, walking through the major parts of an existing project, like the top-level template, how to connect to the I/O pads, and a build workflow.


[11/29/2025 01:30] mithro_
@dshadoff - We did have the 2 * 40 designs from the Google runs.


[11/29/2025 01:38] dshadoff
Not sure how to express my thoughts - but I think a lot of people are not familiar with the world of silicon (beyond FPGAs), and aren't sure what to watch out for (to prevent things from going wrong).  Having a reference project to start with goes a long way


[11/29/2025 01:39] dshadoff
"These inputs produce these outputs"


[11/29/2025 01:39] mithro_
There are a whole bunch of industry best practices but I'm pretty skeptical we know the best way to do things yet.


[11/29/2025 01:39] mithro_
Tiny Tapeout is pretty easy to get started with these days.


[11/29/2025 01:42] dshadoff
In any case, you will likely learn things from the chips received back from this shuttle, which could benefit the next set of submissions.


==============================================================
Exported 17 message(s)
==============================================================